This invention relates to an input drive apparatus of a power transistor utilized for a pulse width modulation (PWM) inverter, or the like.
For causing a power transistor to effect a high speed switching operation it is important to interrupt the power transistors at a high speed. In order to effect such high speed operation it is necessary to pass a large base reverse current for quickly extinguishing charge carriers accumulated in the transistor.
FIG. 1 shows one example of the prior art base drive apparatus of a transistor inverter, in which the circuit bounded by dash and dot lines represents the base drive circuit of a power transistor 10.
The circuit comprises an operating switch 1 connected to a source V.sub.d for producing a forward bias or a reverse bias, a two phase oscillator 2 for producing square wave voltages A and B of opposite phase, two input AND gate circuits 3a and 3b respectively inputted with the output A or B of the two phase oscillator 2 and the output of the switch 1, and an inverter 4 which inverts the output of switch 1 and applies the inverted output to the base electrode of an NPN transistor 5c. The outputs of the AND gate circuits 3a and 3b are applied to the base electrodes of NPN transistors 5a and 5b respectively. The collector electrode of the transistor 5a is connected to the source V.sub.d via the primary winding of a transformer 6a, the collector electrode of the transistor 5b is connected to the source V.sub.d via the primary winding of a transformer 6b, and the collector electrode of the transistor 5c is also connected to the source V.sub.d via the primary winding of the transformer 6c. The emitter electrodes of the transistors 5a, 5b and 5c are commonly grounded.
The upper terminals of the secondary windings of transformers 6a and 6b are connected to the base electrode of a power transistor 10, while the lower terminals of these secondary windings are connected to the emitter electrode of the power transistor 10 respectively through diodes 7a and 7b and a resistor 8a. The upper terminal of the secondary winding of the transformer 6c is connected to the base electrode of an NPN transistor 5d via resistor 8b, while the lower terminal is connected to the emitter electrode of the transistor 5d, the collector electrode thereof being connected to the base electrode of the power transistor 10 via a source 9 of reverse bias voltage. The emitter electrode of the transistor 5d is connected to the emitter electrode of the power transistor 10, and the output of switch 1 is connected to the emitter electrode of transistor 5c through a resistor 8c.
With the circuit described above, when the switch 1 is closed, AND gate circuits 3a and 3b output the logical products of the output of the switch 1 and the outputs A or B of the two phase oscillators 2. While the switch 1 is closed, the outputs of the AND gate circuits 3a and 3b are applied to the base electrodes of the transistors 5a and 5b respectively so as to induce chopped or intermittent square wave voltages in the secondary windings of transformers 6a and 6b. These square wave voltages are rectified by the diodes 7a and 7b respectively and supplied across the base and emitter electrodes of the power transistor 10 for supplying forward bias current through the resistor 8a.
When the switch 1 is opened, an operation opposite to that effected when the switch 1 is closed is performed so that AND gate circuits 3a and 3b are disabled, whereby the supply of the bias voltage to the base electrode of the power transistor 10 is interrupted.
When the switch 1 is opened, the inverter 4 inverts the output of switch 1 to turn ON the transistor 5c. Consequently, the transistor 5d is turned ON through the transformer 6c, and the resistor 8b with the result that a reverse bias current I.sub.B is supplied between the base and emitter electrodes of the power transistor 10 from the source of reverse bias voltage 9 through the transistor 5d.
As above described, in the circuit shown in FIG. 1, for the purpose of turning OFF at a high speed the power transistor 10, the transistor 5d is turned ON to pass large reverse bias current I.sub.B. However, even when the switch 1 is opened, before the charge carriers accumulated in the transistors 5a and 5b are extinguished, the transformers 6a and 6b continue to produce output voltages, and as the transistor 5d has been ON, the source of reverse bias voltage 9 is required to supply a large power.
Even when charge carriers accumulated in the transistors 5a and 5b have been extinguished, the current I.sub.S supplied from the source of reverse bias voltage 9 is divided into reverse bias currents I.sub.R and I.sub.B which also increases the power of the source of reverse bias voltage 9.
Accordingly, in order to decrease the power of the source of reverse bias voltage 9 it is necessary to pass reverse bias current through transistors 5a and 5b so as to shorten as much as possible the time of extinguishing the accumulated charge carriers. Futhermore, it is necessary to make the resistor 8a to have a high resistance so that no reverse current I.sub.R would flow while the switch 1 is open.
Recently, as the capacity of the power transistor (bipolar transistor or FET) 10 has been increased to 50 W or more (when two or more power transistors are connected in parallel, much more output can be obtained) it is necessary to provide a base drive circuit of the power transistor having a simplified construction and which can cut OFF the power transistor 10 at a higher speed.